1. Field of the Invention
The present invention relates generally to resolution enhancement techniques for photolithography and more particularly to techniques for optical proximity correction.
2. Description of the Related Art
A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. The apparatus generally comprises a radiation system for supplying a beam of radiation, a support structure for supporting a patterning device, the patterning device serving to pattern the beam, a substrate table for holding a substrate, and a projection system for projecting the patterned beam of radiation onto a target portion of the substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising part of, one or several dies) on a substrate (e.g., a silicon wafer) that has a layer of radiation-sensitive material (resist). In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at once, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the projection beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
The term “projection system” used herein should be broadly interpreted as encompassing various types of projection system, including refractive optical systems, reflective optical systems, and catadioptric optical systems, as appropriate for example for the exposure radiation being used, or for other factors such as the use of an immersion fluid or the use of a vacuum. Any use of the term “lens” herein may be considered as synonymous with the more general term “projection system.” The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components. The radiation system as well as the projection system generally comprise components for directing, shaping or controlling the projection beam of radiation. Generally, the projection system comprises means to set the numerical aperture (commonly referred to as the “NA”) of the projection system. For example, an adjustable NA-diaphragm can be present in a pupil of the projection system. The radiation system typically comprises adjusting means for setting the outer and/or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution upstream of the mask (in a pupil of the radiation system).
The lithographic apparatus may be of a type having two (dual stage) or more substrate tables (and/or two or more mask tables). In such “multiple stage” machines the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposure. The lithographic apparatus may also be of a type wherein the substrate is immersed in a liquid having a relatively high refractive index, e.g., water, so as to fill a space between the final element of the projection system and the substrate. Immersion liquids may also be applied to other spaces in the lithographic apparatus, for example, between the mask and the first element of the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems.
A circuit pattern corresponding to an individual layer of an IC device generally comprises a plurality of device patterns and interconnecting lines. Device patterns may comprise features of different spatial arrangement such as, for example, line-space patterns (“bar patterns”), capacitor contact patterns, patterns of contact holes and DRAM isolation patterns. A feature is not necessarily characterized by a shape whose line elements define a closed contour. For example, a spatial arrangement of extremities of two neighboring features and a space between the two extremities may also, in the context of the present text and claims, be referred to as a feature.
In the context of the present text and claims, sizes of features are referred to as those sizes that the features nominally have at substrate level. At a mask, the size of a feature is M times larger than the nominal size, where M is the magnification of the projection system (typically, |M|=¼ or ⅕). Generally, additional size deviations at the mask are introduced to compensate for errors occurring, for example, during projection and exposure of a pattern; such a re-sizing of features of the sub-pattern is referred to hereinafter as biasing and/or Optical Proximity Correction (“OPC”). An amount of biasing and/or OPC is also commonly expressed in terms of a corresponding, nominal amount of re-sizing at substrate level. The noun “target” when used in expressions such as “target features” is indicating that these features have substantially a nominal size as desired for the device layer.
One form of OPC is selective bias. Given a CD vs. pitch curve, all of the different pitches could be forced to produce the same CD, at least at best focus and exposure, by changing the CD at the mask level. Thus, if a feature prints too small at the wafer level, the mask level feature would be biased to be slightly larger than nominal, and vice versa. Because the pattern transfer process from mask level to wafer level is nonlinear, the amount of bias is not simply the product of the measured CD error at best focus and exposure time and the reduction ratio, but with modeling and experimentation, an appropriate bias can be determined. Selective bias is an incomplete solution to the problem of proximity effects, particularly if it is only applied at the nominal process condition. Even though such bias could, in principle, be applied to give uniform CD vs. pitch curves at best focus and exposure, once the exposure process varies from the nominal condition, each biased pitch curve will tend to respond differently, resulting gin different process windows for the different features. Therefore, the “best” bias to give identical CD vs. pitch may even have a negative impact on the overall process window, reducing rather than enlarging the focus and exposure range within which all of the target features print on the wafer within the desired process tolerance.
Other more complex OPC techniques have been developed for application beyond the one-dimensional bias example above. A two-dimensional proximity effect is line end shortening. Line ends have a tendency to “pull back” from their desired end point location as a function of exposure and focus. In many cases, the degree of end shortening of a long line end can be several times larger than the corresponding line narrowing. This type of line end pull back can result in catastrophic failure of the devices being manufactured if the line end fails to completely cross over the underlying layer it was intended to cover, such as a polysilicon gate layer over a source-drain region. Since this type of pattern is highly sensitive to focus and exposure, simply biasing the line end to be longer than the design length is inadequate because the line at best focus and exposure, or in an underexposed condition, would be excessively long, resulting either in short circuits as the extended line end touches neighboring structures, or unnecessarily large circuit sizes if more space is added between individual features in the circuit. Since one of the key goals of integrated circuit design and manufacturing is to maximize the number of functional elements while minimizing the area required per chip, adding excess spacing is a highly undesirable solution.
Two-dimensional OPC approaches have been developed to help solve the line end pull back problem. Extra structures (or assist features) known as “hammerheads” or “serifs” are routinely added to line ends to effectively anchor them in place and provide reduced pull back over the entire process window. Even at best focus and exposure these extra structures are not clearly resolved and they alter the appearance of the main feature without being fully resolved on their own. Assist features can take on much more aggressive forms than simple hammerheads added to line ends, to the extent the pattern on the mask is no longer simply the desired wafer pattern upsized by the reduction ratio. Assist features such as serifs can be applied to many more cases than simply reducing line end pull back. Inner or outer serifs can be applied to any edge, especially two dimensional edges, to reduce corner rounding or edge extrusions. With enough selective biasing and assist features of all sizes and polarities, the features on the mask bear less and less of a resemblance to the final pattern desired at the wafer level. In general, the mask pattern becomes a pre-distorted version of the wafer-level pattern, where the distortion is intended to counteract or reverse the pattern deformation that will occur during the lithographic process to produce a pattern on the wafer that is as close to the one intended by the designer as possible.
In another OPC technique, instead of appending assist structures such as serifs to a feature, completely independent and non-resolvable assist features are added to the mask. These independent assist features are not intended or desired to print as features on the wafer, but rather are intended to modify the aerial image of a nearby main feature to enhance the printability and process tolerance of that main feature. Often referred to as “scattering bars,” this type of sub-resolution assist feature (SRAF) adds yet another layer of complexity to a mask. A simple example of a use of scattering bars is where a regular array of non-resolvable scattering bars is drawn on both sides of an isolated line feature, which has the effect of making the isolated line appear, from an aerial image standpoint, to be more representative of a single line within an array of dense lines, resulting in a process window much closer in focus and exposure tolerance to that of a dense pattern. The common process window between such a decorated isolated feature and a dense pattern will have a larger common tolerance to focus and exposure variations than that of a feature drawn as isolated at the mask level.
Many of these OPC techniques may be used together on a single mask with phase-shifting structures of different phases added in as well for both resolution and process window enhancement. The simple task of biasing a one-dimensional line becomes increasingly complicated as two-dimensional structures must be moved, resized, enhanced with assist features, and possibly phase-shifted without causing any conflict with adjoining features. Due to the extended proximity range of deep sub-wavelength lithography, changes in the type of OPC applied to a feature can have unintended consequences for another feature located within half a micron to a micron. Since there are likely to be many features within this proximity range, the task of optimizing OPC decoration becomes increasingly complex with the addition of more aggressive approaches. Each new feature that is added to a design has an effect on other features, which then must be re-corrected in turn, and the results must be iterated repeatedly to converge to a mask layout where each feature can be printed in the manner in which it was originally intended while at the same time contributing in the proper manner to the aerial images of its neighboring features such that they too are printed within their respective tolerances.
Due to this complexity and mutual interaction between features, OPC technology has become a major field of innovation and many techniques have been widely described on how to “segment” or “dissect” the features into a manageable number of edges for co-optimization, how to prioritize the optimization routines so that the most critical structures are best protected from unintended distortion by nearby OPC assist features on neighboring features, how to resolve phase and placement conflicts between features, how to trade off computational speed versus ultimate convergence of the resulting feature to the desired results, and other details of the full implementation of OPC as a manufacturable technology.
OPC has generally moved from a rule-based to a model-based approach. In model-based OPC, both the effect of the exposure tool on the aerial image and the effect of the resist processing are modeled mathematically. In a model based design process, a pre-OPC layout, an OPC technology file, an optical model, and a resist model are obtained. The OPC technology file describes the types of model based OPC techniques that are to be used, for example linewidth bias corrections, corner rounding corrections, or line end pull back corrections. The optical model describes the illumination and projection optics of the exposure tool. The optical model may also include the effect of imaging into a thin-film resist or the effect of the mask topography. The resist model describes the changes in the resist after being illuminated by the mask pattern in the exposure tool. An etch model may also be used in this type of method. The optical, resist, and etch models can be derived from first principles, determined empirically from experimental data, or a combination of both. The models are usually calibrated at the nominal process condition. See R. Socha, “Resolution Enhancement Techniques,” Photomask Fabrication Technology, Benjamin G. Eynon, Jr. and Banqiu Wu, Editors, McGraw-Hill, pp. 466-468, 2005. The pre-OPC layout, the OPC technology file, and the models are all inputs to the model-based OPC software.
The model-based OPC software segments the features in the pre-OPC layout into edge segments and assigns control points to each edge segment. Each feature is segmented prior to applying any OPC techniques because each feature, even identically-shaped features, will be subject to different proximity environments. The control points (or evaluation points) are the locations where CD or edge placement errors (EPE) will be evaluated during the OPC design process. The assignment of the control points is a complex process that depends on the pattern geometry of the pre-OPC layout and the optical model.
The model-based OPC software proceeds by simulating the printed resist image on the wafer by applying the optical model and the resist model to the pre-OPC layout. In general, the simulation is performed at the nominal process condition at which the optical model has been calibrated. The model-based OPC software then generates the contours of the simulated resist image by comparing the simulated resist image values to a selected threshold value. The model-based OPC software then compares the simulated contours with the pre-OPC layout at the control points to determine if the design layout will deliver the desired patterning performance. The comparisons are typically quantified as a CD or an EPE at each control point. The model-based OPC software then determines whether a figure of merit for the contour metric of each edge segment is satisfied. In one embodiment, the figure of merit is satisfied when the total error for the contour metric, e.g., CD or EPE, of each edge segment is minimized. In another embodiment, the figure of merit is satisfied when the total error for the contour metric of each edge segment is below a predetermined threshold. If the figure of merit is satisfied the process ends, but if the figure of merit is not satisfied, the process continues with a new iteration.
If the EPE of the i-th edge segment (Ei) is ΔEi determined at the control point CPi, the simplest edge correction amount ΔCi is a negation of the error: ΔCi=ΔEi. Such a straightforward correction function does not work well for nonlinear processes because changes on the mask are not linearly reflected in the printed resist image. To account for nonlinearities such as the mask error factor (MEF), a slightly more complicated correction function can be used:ΔCi=−Ei/MEF  (1)
In a particular application, the method of calculating the appropriate correction tends to be much more complex, and the correction algorithms can depend on factors such as linewidth error, fabrication process, correction goals, and constraints. See A. K. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE Press, pp. 91-115, 2001. For example, if it is assumed that there are n edge segments of a feature and one control point for each edge segment, and that the total correction amount for the i-th edge segment is Ci, the ultimate goal is to solve for C1, C2, . . . , Cn iteratively, such that the difference between resist image values RI(CPi) and the predetermined threshold values Tat all control points are equal to zero as: RI(CPi)−T=0 for i=1, . . . , n, where CPi are the control points. Alternately, one can minimize the function:
                              ∑                      i            =            1                    n                ⁢                              [                                          RI                ⁡                                  (                                      CP                    i                                    )                                            -              T                        ]                    2                                    (        2        )            
Next, at each iteration, the model-based OPC software adjusts the entire edge segment Ei according to the calculated correction amount ΔCi for all edge segments to produce a post-OPC layout, such that the simulated resist image contour moves to match the design geometry. Then the model-based OPC software simulates a resist image using the post-OPC layout. The resist image contours and error are then calculated for the simulated resist image produced using the post-OPC layout. The model-based OPC software determines whether the total EP error is minimized or below a certain threshold. The total EP error may be defined as:
                              Error          total                =                              ∑                          i              =              1                        n                    ⁢                                    (                              Δ                ⁢                                                                  ⁢                                  E                  i                                            )                        2                                              (        3        )            
Alternatively, the total EP error can be defined as the maximum EP error of all segments, i.e.:max{|ΔEi|}, i=1, . . . , n  (4)because the OPC goal may be set such that all edge placement errors must be below a certain threshold.
A correction amount is determined individually for each edge segment in the mask layout, without taking into account effects from the movements of other edge segments in the layout. As feature size decreases, solving for the correction amount for individual edge segments experiences convergence problems.
A multivariable solver for OPC has been disclosed in U.S. patent application Ser. No. 11/764,128, herein incorporated by reference in its entirety. In the method described, effects on resist image values at a plurality of edge segments of collective movement of edge segments in a mask layout are tracked. Control points and edge segments are defined for a number of contact features. As contact features tend to be relatively small, moving an edge segment affects the resist image value at that edge segment's control point and also affects the resist image values at the control points of other edge segments of the contact feature. For contact features that are placed close together in the layout, moving an edge segment of one contact feature also affects the resist image values at the control points of edge segments in neighboring contact features. Similar effects on resist image values at control points due to movements of neighboring edge segments can be observed in mask layouts for non-contact layers.
In accordance with an embodiment, the layout is first subdivided into patches, which are typically 20 μm×20 μm to 60 μm×60 μm in area, before applying OPC. After OPC has been applied, the patches are combined together to produce the final post-OPC layout. Then, a resist image (RI) is simulated using a design layout (pre-OPC layout). The resist image may be simulated using a photolithography simulation system such as that disclosed in U.S. Pat. No. 7,003,758, the subject matter of which is hereby incorporated by reference in its entirety. Assuming there exist n movable edge segments, the edge segments in the design layout are perturbed (i.e., moved) by a predetermined distance, which is specified by the n×1 vector ΔC0, to produce a perturbed layout. By convention, vectorial quantities and matrices are denoted by bold-faced characters throughout this document. A resist image is then simulated using the perturbed layout.
A difference between the simulated RI values produced using the design layout and the simulated RI values produced using the perturbed layout are determined for each edge segment. These differences are used to create an initial matrix, J0. The initial matrix is an n×n matrix, where n is the number of edge segments in the layout, which for some masks can be more than a million. The initial matrix is a diagonal matrix in which the i-th diagonal entry, where i=1, . . . , n, is computed as the differences between the simulated RI values of the i-th segment ΔRIi divided by the amount of the perturbation of the i-th segment ΔCi0. Mathematically, the i-th diagonal entry of J0 is given by:[J0]ii=ΔRIi/ΔCi0  (n)
In other words, initially it is assumed that the edge segments do not interact. Changes in each edge segment's RI value are attributed to that edge segment only. As a diagonal matrix, the off-diagonal elements of J0 are identically zero. That is, [J0]ij=0 for i≠j.
As described in U.S. patent application Ser. No. 11/764,128, a correction delta vector is determined based on the pseudo inverse of the matrix. A damping factor is applied to the correction delta vector and edge segments are each moved by the damped correction delta. A simulated resist image is generated using the updated edge segments. Finally, the matrix is updated based on changes in the simulated resist image values and the correction delta. At this point, one iteration is complete. The method may be further iterated for a selected number of iterations, or the resulting layout achieves a figure of merit. As an example, the figure of merit may be satisfied when a sum of edge placement errors is minimized (e.g., by a least squares method) or when such a sum is below a predetermined threshold. If the figure of merit is not achieved, the method is re-iterated. Upon completion, the resulting design may be used to manufacture a mask, or may be used in computer simulations for other process design activities that require a mask pattern as an input.
In this approach, it can occur that a selected number of iterations is insufficient to estimate all the unknowns in the full Jacobian matrix. Also, depending on the geometry of the mask, the solution may fail to converge to a complete solution due to the presence of a local minimum. As a result, alternate approaches may be useful.